The present invention relates to computer systems; more particularly, the present invention relates to the resolution of bank conflicts between memory accesses in high performance microprocessors.
Due to the difference in cycle time between microprocessors and main memory in a computer system, microprocessors typically implement one or more cache memories (cache). A cache is a small, fast intermediary memory device that typically only includes data and instructions most recently used. In some designs caches include multiple banks in order to enable multiple accesses to be performed during each clock cycle. A multiple bank cache is divided such that datum can be stored in one bank. Each bank allows for one access each clock cycle. An interconnection network is implemented to route each instruction/datum to the correct bank.
Moreover, a cache may employ non-blocking behavior that allows multiple misses from higher-level caches to be pending. Non-blocking behavior also enables a microprocessor core to continue execution until requested data can be retrieved and used. The multiple miss requests are usually stored in a queue structure. For example, if there are multiple misses in a first level (e.g., L1) cache, the misses are stored in a queue that needs access to a second level (e.g., L2) cache. Entries from the queue can be used to access the L2 cache in a first in first out (FIFO) scheme or an out-of-order scheme.
However, in order to increase queue bandwidth, multiple ports from the queue may access the bank array. The multiple ports may have miss requests that attempt to simultaneously access the same banks in the cache, thus, leading to conflicts.